The present invention relates to an image processing apparatus having an affine conversion for performing reduction, enlargement, and rotation of an image.
According to affine conversion as one of the functions of an image processing apparatus, an image stored in a read (input) image memory is reduced, enlarged, or rotated and is output to a write (output) image memory. An image processing apparatus having the affine conversion function conventionally has an arrangement as shown in FIG. 1. By the affine conversion of the image processing apparatus shown in FIG. 1, image data is written in write image memory 11 in accordance with a raster operation. The image data is read out from an address (X, Y) of read image memory 12 that corresponds to the raster address (I, J) of write image memory 11. Address (X, Y) is calculated by affine conversion address generator 13 in accordance with the following equations: EQU X=aI+bJ+c ...(1) EQU Y=dI+eJ+f ...(2)
where a, b, c, d, e, and f are constants.
Address generator 13 calculates address (X, Y) of memory 12 that corresponds to address (I, J) of memory 11 and outputs it onto address bus 21 of control bus 20 as an image input read address, as shown in FIG. 2A. In this case, address generator 13 supplies a read signal onto read signal line 23 of control bus 20. In response to the read signal received from control bus 20, image data is read out from a pixel position of memory 12 designated by address (X, Y) input through address bus 21.
The image data read out from memory 12, i.e., the image data at the position of address (X, Y) is supplied to data bus 22 of control bus 20, as shown in FIG. 2B. Address generator 13 fetches and latches the image data on data bus 22. In the next cycle, address generator 13 outputs the latched data onto data bus 22 and address (I, J) of memory 11 onto address bus 21 (see FIG. 2A). At the same time, address generator 13 supplies a write signal onto write signal line 24 of control bus 20. In response to the write signal, data input through data bus 22 is written at a pixel position of memory 11 designated by address (I, J) input through address bus 21. The above operation is repeated every 2 bus cycles (2T) of control bus 20 while raster address (I, J) is being updated.
In this manner, affine conversion address generator 13 of the conventional image processing apparatus shown in FIG. 1 requires 2 cycles for one-pixel affine conversion, that is, a read cycle for transferring affine conversion address (X, Y) to read image memory 12 together with a read signal and reading image data from memory 12, and a write cycle for transferring the read image data to write image memory 11 together with raster address (I, J) and a write signal and enabling writing to memory 11. Therefore, the conventional image processing apparatus cannot perform high-speed affine conversion.